Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2902540
date_generatedWed May 27 16:50:49 2026 os_platformWIN64
product_versionVivado v2020.1 (64-bit) project_id96bdc0e9e48f41a4a2ba06387fa64912
project_iteration3 random_id6fdd8ce6ee615385a8f69e4b0a4aa476
registration_id6fdd8ce6ee615385a8f69e4b0a4aa476 route_designTRUE
target_devicexc7a200t target_familyartix7
target_packagefbg484 target_speed-1
tool_flowVivado

user_environment
cpu_name13th Gen Intel(R) Core(TM) i5-13420H cpu_speed2611 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram16.000 GB total_processors1

vivado_usage
gui_handlers
basedialog_cancel=2 basedialog_ok=14 basedialog_yes=1 constraintschooserpanel_add_files=1
coretreetablepanel_core_tree_table=6 filesetpanel_file_set_panel_tree=15 flownavigatortreepanel_flow_navigator_tree=23 fpgachooser_fpga_table=1
gettingstartedview_create_new_project=1 mainmenumgr_window=2 mainwintoolbarmgr_select_or_save_window_layout=2 pacommandnames_add_sources=1
pacommandnames_auto_connect_target=1 pacommandnames_auto_update_hier=3 pacommandnames_fileset_window=1 pacommandnames_goto_netlist_design=1
pacommandnames_run_bitgen=2 paviews_project_summary=2 programdebugtab_open_target=1 programdebugtab_program_device=2
programfpgadialog_program=2 progressdialog_cancel=1 projectnamechooser_choose_project_location=1 projectnamechooser_project_name=1
signaltreepanel_signal_tree_table=1 simpleoutputproductdialog_generate_output_products_immediately=1 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=9 srcmenu_ip_hierarchy=3
syntheticagettingstartedview_recent_projects=1 touchpointsurveydialog_no=2
java_command_handlers
addsources=3 autoconnecttarget=1 coreview=1 customizecore=1
fileexit=2 launchprogramfpga=2 newproject=1 openhardwaremanager=1
runbitgen=3 runimplementation=3 runsynthesis=2 showview=2
timingconstraintswizard=1 viewlayoutcmd=2 viewtaskimplementation=1 viewtasksynthesis=1
other_data
guimode=2
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=1 export_simulation_ies=1
export_simulation_modelsim=1 export_simulation_questa=1 export_simulation_riviera=1 export_simulation_vcs=1
export_simulation_xsim=1 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=26 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=2 totalsynthesisruns=2

unisim_transformation
post_unisim_transformation
bufg=8 carry4=21 fdce=28 fdre=230
fdse=1 gnd=30 ibuf=7 lut1=64
lut2=57 lut3=31 lut4=35 lut5=51
lut6=39 muxf7=5 muxf8=1 obuf=7
obuft=2 plle2_adv=1 ramb18e1=3 vcc=27
pre_unisim_transformation
bufg=8 carry4=21 fdce=28 fdre=230
fdse=1 gnd=30 ibuf=5 iobuf=2
lut1=64 lut2=57 lut3=31 lut4=35
lut5=51 lut6=39 muxf7=5 muxf8=1
obuf=7 plle2_adv=1 ramb18e1=3 vcc=27

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] -bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] -directive=default::[not_specified] -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] -hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] -restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] -uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=4 bram_ports_total=6 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=178 srls_augmented=0
srls_newly_gated=0 srls_total=0

ip_statistics
clk_wiz_v6_0_5_0_0/1
clkin1_period=10.000 clkin2_period=10.000 clock_mgr_type=NA component_name=DCM_Audio
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=2 primitive=PLL
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1 check-3=1 reqp-1840=20

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
lutar-1=1 timing-17=187 xdcc-1=1

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.000160 clocks=0.000000
confidence_level_clock_activity=Low confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=Low confidence_level_overall=Low customer=TBD customer_class=TBD
devstatic=0.138647 die=xc7a200tfbg484-1 dsp_output_toggle=12.500000 dynamic=0.065618
effective_thetaja=2.47 enable_probability=0.990000 family=artix7 ff_toggle=12.500000
flow_state=routed heatsink=medium (Medium Profile) i/o=0.013365 input_toggle=12.500000
junction_temp=25.5 (C) logic=0.000901 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 netlist_net_matched=NA off-chip_power=0.000000
on-chip_power=0.204265 output_enable=1.000000 output_load=5.000000 output_toggle=12.500000
package=fbg484 pct_clock_constrained=0.000000 pct_inputs_defined=0 platform=nt64
pll=0.050237 process=typical ram_enable=50.000000 ram_write=50.000000
read_saif=False set/reset_probability=0.000000 signal_rate=False signals=0.000954
simulation_file=None speedgrade=-1 static_prob=False temp_grade=commercial
thetajb=4.8 (C/W) thetasa=4.2 (C/W) toggle_rate=False user_board_temp=25.0 (C)
user_effective_thetaja=2.47 user_junc_temp=25.5 (C) user_thetajb=4.8 (C/W) user_thetasa=4.2 (C/W)
vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000
vccaux_dynamic_current=0.028114 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000 vccaux_static_current=0.030521 vccaux_total_current=0.058635 vccaux_voltage=1.800000
vccbram_dynamic_current=0.000012 vccbram_static_current=0.000763 vccbram_total_current=0.000775 vccbram_voltage=1.000000
vccint_dynamic_current=0.002560 vccint_static_current=0.030447 vccint_total_current=0.033007 vccint_voltage=1.000000
vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000
vcco33_dynamic_current=0.003770 vcco33_static_current=0.005000 vcco33_total_current=0.008770 vcco33_voltage=3.300000
version=2020.1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=5 bufgctrl_util_percentage=15.63
bufhce_available=120 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=40 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=20 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=40 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=10 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=10 plle2_adv_fixed=0 plle2_adv_used=1 plle2_adv_util_percentage=10.00
dsp
dsps_available=740 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=365 block_ram_tile_fixed=0 block_ram_tile_used=1.5 block_ram_tile_util_percentage=0.41
ramb18_available=730 ramb18_fixed=0 ramb18_used=3 ramb18_util_percentage=0.41
ramb18e1_only_used=3 ramb36_fifo_available=365 ramb36_fifo_fixed=0 ramb36_fifo_used=0
ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=5 carry4_functional_category=CarryLogic carry4_used=21
fdce_functional_category=Flop & Latch fdce_used=33 fdre_functional_category=Flop & Latch fdre_used=149
fdse_functional_category=Flop & Latch fdse_used=1 ibuf_functional_category=IO ibuf_used=6
lut1_functional_category=LUT lut1_used=28 lut2_functional_category=LUT lut2_used=55
lut3_functional_category=LUT lut3_used=50 lut4_functional_category=LUT lut4_used=35
lut5_functional_category=LUT lut5_used=28 lut6_functional_category=LUT lut6_used=36
muxf7_functional_category=MuxFx muxf7_used=2 muxf8_functional_category=MuxFx muxf8_used=1
obuf_functional_category=IO obuf_used=7 obuft_functional_category=IO obuft_used=2
plle2_adv_functional_category=Clock plle2_adv_used=1 ramb18e1_functional_category=Block Memory ramb18e1_used=3
slice_logic
f7_muxes_available=66900 f7_muxes_fixed=0 f7_muxes_used=2 f7_muxes_util_percentage=<0.01
f8_muxes_available=33450 f8_muxes_fixed=0 f8_muxes_used=1 f8_muxes_util_percentage=<0.01
lut_as_logic_available=133800 lut_as_logic_fixed=0 lut_as_logic_used=185 lut_as_logic_util_percentage=0.14
lut_as_memory_available=46200 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=267600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=183 register_as_flip_flop_util_percentage=0.07
register_as_latch_available=267600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=133800 slice_luts_fixed=0 slice_luts_used=185 slice_luts_util_percentage=0.14
slice_registers_available=267600 slice_registers_fixed=0 slice_registers_used=183 slice_registers_util_percentage=0.07
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=133800 lut_as_logic_fixed=0
lut_as_logic_used=185 lut_as_logic_util_percentage=0.14 lut_as_memory_available=46200 lut_as_memory_fixed=0
lut_as_memory_used=0 lut_as_memory_util_percentage=0.00 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 lut_in_front_of_the_register_is_unused_used=11 lut_in_front_of_the_register_is_used_fixed=11 lut_in_front_of_the_register_is_used_used=8
register_driven_from_outside_the_slice_fixed=8 register_driven_from_outside_the_slice_used=19 register_driven_from_within_the_slice_fixed=19 register_driven_from_within_the_slice_used=164
slice_available=33450 slice_fixed=0 slice_registers_available=267600 slice_registers_fixed=0
slice_registers_used=183 slice_registers_util_percentage=0.07 slice_used=80 slice_util_percentage=0.24
slicel_fixed=0 slicel_used=47 slicem_fixed=0 slicem_used=33
unique_control_sets_available=33450 unique_control_sets_fixed=33450 unique_control_sets_used=19 unique_control_sets_util_percentage=0.06
using_o5_and_o6_fixed=0.06 using_o5_and_o6_used=47 using_o5_output_only_fixed=47 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=138
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=default::default -fanout_limit=default::10000
-flatten_hierarchy=default::rebuilt -fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1
-max_dsp=default::-1 -max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default
-name=default::[not_specified] -no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified]
-part=xc7a200tfbg484-1 -resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified]
-rtl_skip_constraints=default::[not_specified] -rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified]
-shreg_min_size=default::3 -top=MusicPLayerTop -verilog_define=default::[not_specified]
usage
elapsed=00:00:24s hls_ip=0 memory_gain=94.230MB memory_peak=1121.461MB