#-----------------------------------------------------------
# Vivado v2020.1 (64-bit)
# SW Build 2902540 on Wed May 27 19:54:49 MDT 2020
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
# Start of session at: Wed May 27 16:49:26 2026
# Process ID: 9172
# Current directory: D:/DigitalSystem/lab19_MusicPlayer/vivado/MusicPlayer.runs/impl_1
# Command line: vivado.exe -log MusicPLayerTop.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source MusicPLayerTop.tcl -notrace
# Log file: D:/DigitalSystem/lab19_MusicPlayer/vivado/MusicPlayer.runs/impl_1/MusicPLayerTop.vdi
# Journal file: D:/DigitalSystem/lab19_MusicPlayer/vivado/MusicPlayer.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source MusicPLayerTop.tcl -notrace
Command: link_design -top MusicPLayerTop -part xc7a200tfbg484-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7a200tfbg484-1
INFO: [Project 1-454] Reading design checkpoint 'd:/DigitalSystem/lab19_MusicPlayer/vivado/MusicPlayer.srcs/sources_1/ip/DCM_Audio/DCM_Audio.dcp' for cell 'DCM_inst'
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1025.434 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 33 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2020.1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [d:/DigitalSystem/lab19_MusicPlayer/vivado/MusicPlayer.srcs/sources_1/ip/DCM_Audio/DCM_Audio_board.xdc] for cell 'DCM_inst/inst'
Finished Parsing XDC File [d:/DigitalSystem/lab19_MusicPlayer/vivado/MusicPlayer.srcs/sources_1/ip/DCM_Audio/DCM_Audio_board.xdc] for cell 'DCM_inst/inst'
Parsing XDC File [d:/DigitalSystem/lab19_MusicPlayer/vivado/MusicPlayer.srcs/sources_1/ip/DCM_Audio/DCM_Audio.xdc] for cell 'DCM_inst/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/DigitalSystem/lab19_MusicPlayer/vivado/MusicPlayer.srcs/sources_1/ip/DCM_Audio/DCM_Audio.xdc:57]
INFO: [Timing 38-2] Deriving generated clocks [d:/DigitalSystem/lab19_MusicPlayer/vivado/MusicPlayer.srcs/sources_1/ip/DCM_Audio/DCM_Audio.xdc:57]
get_clocks: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 1419.133 ; gain = 393.699
Finished Parsing XDC File [d:/DigitalSystem/lab19_MusicPlayer/vivado/MusicPlayer.srcs/sources_1/ip/DCM_Audio/DCM_Audio.xdc] for cell 'DCM_inst/inst'
Parsing XDC File [D:/DigitalSystem/lab19_MusicPlayer/src/MusicPlayer.xdc]
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [D:/DigitalSystem/lab19_MusicPlayer/src/MusicPlayer.xdc:1]
Finished Parsing XDC File [D:/DigitalSystem/lab19_MusicPlayer/src/MusicPlayer.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1419.156 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 2 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 2 instances

11 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:14 . Memory (MB): peak = 1419.156 ; gain = 393.723
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.755 . Memory (MB): peak = 1419.156 ; gain = 0.000

Starting Cache Timing Information Task
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [D:/DigitalSystem/lab19_MusicPlayer/src/MusicPlayer.xdc:1]
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1f31b5c79

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1438.320 ; gain = 19.164

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 2 inverter(s) to 27 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 208112443

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1629.863 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 26 cells and removed 62 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 153f7ee8f

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 1629.863 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 1 cells and removed 17 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 1c3920470

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.103 . Memory (MB): peak = 1629.863 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 80 cells

Phase 4 BUFG optimization
INFO: [Opt 31-274] Optimized connectivity to 3 cascaded buffer cells
Phase 4 BUFG optimization | Checksum: 1d51bbc80

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.114 . Memory (MB): peak = 1629.863 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 3 cells.

Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: 1d51bbc80

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.120 . Memory (MB): peak = 1629.863 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 1c752a399

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.123 . Memory (MB): peak = 1629.863 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |              26  |              62  |                                              0  |
|  Constant propagation         |               1  |              17  |                                              0  |
|  Sweep                        |               0  |              80  |                                              0  |
|  BUFG optimization            |               0  |               3  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1629.863 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 1e810ec81

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.141 . Memory (MB): peak = 1629.863 ; gain = 0.000

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [D:/DigitalSystem/lab19_MusicPlayer/src/MusicPlayer.xdc:1]
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 3 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 4 Total Ports: 6
Number of Flops added for Enable Generation: 5

Ending PowerOpt Patch Enables Task | Checksum: 29f6cea2a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1736.820 ; gain = 0.000
Ending Power Optimization Task | Checksum: 29f6cea2a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.529 . Memory (MB): peak = 1736.820 ; gain = 106.957

Starting Final Cleanup Task

Starting Logic Optimization Task
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [D:/DigitalSystem/lab19_MusicPlayer/src/MusicPlayer.xdc:1]
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Logic Optimization Task | Checksum: 22ea704f6

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1736.820 ; gain = 0.000
Ending Final Cleanup Task | Checksum: 22ea704f6

Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1736.820 ; gain = 0.000

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1736.820 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 22ea704f6

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1736.820 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
38 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [D:/DigitalSystem/lab19_MusicPlayer/src/MusicPlayer.xdc:1]
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1736.820 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'D:/DigitalSystem/lab19_MusicPlayer/vivado/MusicPlayer.runs/impl_1/MusicPLayerTop_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file MusicPLayerTop_drc_opted.rpt -pb MusicPLayerTop_drc_opted.pb -rpx MusicPLayerTop_drc_opted.rpx
Command: report_drc -file MusicPLayerTop_drc_opted.rpt -pb MusicPLayerTop_drc_opted.pb -rpx MusicPLayerTop_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file D:/DigitalSystem/lab19_MusicPlayer/vivado/MusicPlayer.runs/impl_1/MusicPLayerTop_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[10] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[6]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[16]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[10] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[6]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[11] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[7]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[17]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[11] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[7]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[12] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[8]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[18]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[12] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[8]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[13] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[9]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[19]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[13] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[9]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[4] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[0]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[4] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[0]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[5] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[1]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[5] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[1]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[6] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[2]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[6] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[2]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[7] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[3]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[7] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[3]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[8] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[4]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[8] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[4]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[9] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[5]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[9] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[5]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 21 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1736.820 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1c5dc699c

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1736.820 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1736.820 ; gain = 0.000

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 8ff73fe9

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.732 . Memory (MB): peak = 1736.820 ; gain = 0.000

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 926ca2d3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.782 . Memory (MB): peak = 1736.820 ; gain = 0.000

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 926ca2d3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.786 . Memory (MB): peak = 1736.820 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 926ca2d3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.798 . Memory (MB): peak = 1736.820 ; gain = 0.000

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 926ca2d3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.807 . Memory (MB): peak = 1736.820 ; gain = 0.000

Phase 2.2 Global Placement Core
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
Phase 2.2 Global Placement Core | Checksum: 82fb9c1f

Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1736.820 ; gain = 0.000
Phase 2 Global Placement | Checksum: 82fb9c1f

Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1736.820 ; gain = 0.000

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 82fb9c1f

Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1736.820 ; gain = 0.000

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1318013c3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1736.820 ; gain = 0.000

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 6f453ee9

Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1736.820 ; gain = 0.000

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 6f453ee9

Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1736.820 ; gain = 0.000

Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: b5ad307e

Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1736.820 ; gain = 0.000

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: b5ad307e

Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1736.820 ; gain = 0.000

Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: b5ad307e

Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1736.820 ; gain = 0.000
Phase 3 Detail Placement | Checksum: b5ad307e

Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1736.820 ; gain = 0.000

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: b5ad307e

Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1736.820 ; gain = 0.000

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: b5ad307e

Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1736.820 ; gain = 0.000

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: b5ad307e

Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1736.820 ; gain = 0.000

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1736.820 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 14bef90db

Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1736.820 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 14bef90db

Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1736.820 ; gain = 0.000
Ending Placer Task | Checksum: 129ad78b0

Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1736.820 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
55 Infos, 22 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.072 . Memory (MB): peak = 1736.820 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'D:/DigitalSystem/lab19_MusicPlayer/vivado/MusicPlayer.runs/impl_1/MusicPLayerTop_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file MusicPLayerTop_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1736.820 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file MusicPLayerTop_utilization_placed.rpt -pb MusicPLayerTop_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file MusicPLayerTop_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1736.820 ; gain = 0.000
Command: phys_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
63 Infos, 22 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.096 . Memory (MB): peak = 1736.820 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'D:/DigitalSystem/lab19_MusicPlayer/vivado/MusicPlayer.runs/impl_1/MusicPLayerTop_physopt.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 4e14161c ConstDB: 0 ShapeSum: db996294 RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: b9a591d5

Time (s): cpu = 00:00:16 ; elapsed = 00:00:37 . Memory (MB): peak = 1881.711 ; gain = 144.891
Post Restoration Checksum: NetGraph: 8434fc3f NumContArr: 35709596 Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: b9a591d5

Time (s): cpu = 00:00:16 ; elapsed = 00:00:37 . Memory (MB): peak = 1881.711 ; gain = 144.891

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: b9a591d5

Time (s): cpu = 00:00:16 ; elapsed = 00:00:37 . Memory (MB): peak = 1889.156 ; gain = 152.336

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: b9a591d5

Time (s): cpu = 00:00:16 ; elapsed = 00:00:37 . Memory (MB): peak = 1889.156 ; gain = 152.336
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 751937b1

Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1929.441 ; gain = 192.621
Phase 2 Router Initialization | Checksum: 751937b1

Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1929.441 ; gain = 192.621

Router Utilization Summary
  Global Vertical Routing Utilization    = 0 %
  Global Horizontal Routing Utilization  = 0 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 344
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 344
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0


Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 10d6dff96

Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1929.441 ; gain = 192.621

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 23
 Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: ddfaf591

Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1929.441 ; gain = 192.621
Phase 4 Rip-up And Reroute | Checksum: ddfaf591

Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1929.441 ; gain = 192.621

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: ddfaf591

Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1929.441 ; gain = 192.621

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: ddfaf591

Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1929.441 ; gain = 192.621
Phase 5 Delay and Skew Optimization | Checksum: ddfaf591

Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1929.441 ; gain = 192.621

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: ddfaf591

Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1929.441 ; gain = 192.621
Phase 6.1 Hold Fix Iter | Checksum: ddfaf591

Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1929.441 ; gain = 192.621
Phase 6 Post Hold Fix | Checksum: ddfaf591

Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1929.441 ; gain = 192.621

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.0213787 %
  Global Horizontal Routing Utilization  = 0.0201586 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: ddfaf591

Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1929.441 ; gain = 192.621

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: ddfaf591

Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1929.441 ; gain = 192.621

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 151c8a3c5

Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1929.441 ; gain = 192.621

Phase 10 Post Router Timing
Phase 10 Post Router Timing | Checksum: 151c8a3c5

Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1929.441 ; gain = 192.621
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1929.441 ; gain = 192.621

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
72 Infos, 22 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:39 . Memory (MB): peak = 1929.441 ; gain = 192.621
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1929.441 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'D:/DigitalSystem/lab19_MusicPlayer/vivado/MusicPlayer.runs/impl_1/MusicPLayerTop_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file MusicPLayerTop_drc_routed.rpt -pb MusicPLayerTop_drc_routed.pb -rpx MusicPLayerTop_drc_routed.rpx
Command: report_drc -file MusicPLayerTop_drc_routed.rpt -pb MusicPLayerTop_drc_routed.pb -rpx MusicPLayerTop_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file D:/DigitalSystem/lab19_MusicPlayer/vivado/MusicPlayer.runs/impl_1/MusicPLayerTop_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file MusicPLayerTop_methodology_drc_routed.rpt -pb MusicPLayerTop_methodology_drc_routed.pb -rpx MusicPLayerTop_methodology_drc_routed.rpx
Command: report_methodology -file MusicPLayerTop_methodology_drc_routed.rpt -pb MusicPLayerTop_methodology_drc_routed.pb -rpx MusicPLayerTop_methodology_drc_routed.rpx
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [D:/DigitalSystem/lab19_MusicPlayer/src/MusicPlayer.xdc:1]
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file D:/DigitalSystem/lab19_MusicPlayer/vivado/MusicPlayer.runs/impl_1/MusicPLayerTop_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file MusicPLayerTop_power_routed.rpt -pb MusicPLayerTop_power_summary_routed.pb -rpx MusicPLayerTop_power_routed.rpx
Command: report_power -file MusicPLayerTop_power_routed.rpt -pb MusicPLayerTop_power_summary_routed.pb -rpx MusicPLayerTop_power_routed.rpx
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [D:/DigitalSystem/lab19_MusicPlayer/src/MusicPlayer.xdc:1]
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
86 Infos, 22 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file MusicPLayerTop_route_status.rpt -pb MusicPLayerTop_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file MusicPLayerTop_timing_summary_routed.rpt -pb MusicPLayerTop_timing_summary_routed.pb -rpx MusicPLayerTop_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file MusicPLayerTop_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file MusicPLayerTop_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file MusicPLayerTop_bus_skew_routed.rpt -pb MusicPLayerTop_bus_skew_routed.pb -rpx MusicPLayerTop_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
Command: write_bitstream -force MusicPLayerTop.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[10] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[6]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[16]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[10] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[6]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[11] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[7]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[17]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[11] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[7]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[12] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[8]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[18]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[12] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[8]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[13] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[9]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[19]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[13] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[9]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[4] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[0]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[4] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[0]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[5] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[1]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[5] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[1]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[6] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[2]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[6] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[2]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[7] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[3]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[7] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[3]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[8] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[4]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[8] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[4]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[9] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[5]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 music_player_inst/note_player_inst/dds_inst/rom/dout_reg has an input control pin music_player_inst/note_player_inst/dds_inst/rom/dout_reg/ADDRARDADDR[9] (net: music_player_inst/note_player_inst/dds_inst/rom/ADDRARDADDR[5]) which is driven by a register (music_player_inst/note_player_inst/dds_inst/dff1/Q_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 22 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./MusicPLayerTop.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
105 Infos, 44 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 2398.605 ; gain = 466.145
INFO: [Common 17-206] Exiting Vivado at Wed May 27 16:50:50 2026...
